Analog to digital converters (ADC) in wireless receiver circuits are often designed with specific and fixed requirements beforehand, such as conversion resolution and conversion speed for following digital signal processing. The ADC circuitry area and power consumption are typically determined from the architecture and design according to the resolution and speed requirements. Accordingly, the ADC is not optimized for power or performance. It is desirable to be able to utilize an ADC in a manner that allows an associated circuit to consume less power during idle operation, while also allowing the ADC to perform at a high rate, resolution or speed when the ADC is in use. The present invention addresses such a need.